Current demands for high density and performance associated with ultra large scale integration require submicron features of about 0.18 microns and under, increased transistor and circuit speeds and improved reliability. Such demands for increased density, performance and reliability require formation of device features with high precision and uniformity. Consequently, the need for device optimization, including accurate measuring of device electrical characteristics, has become increasingly critical.
Metal oxide semiconductor (MOS) devices, as depicted in FIG. 1, are the building blocks of today's circuits, and typically comprise a pair of active regions 110 (also called source/drain regions) formed, as by ion implantation, in a silicon substrate 100, and separated by an ion-implanted channel region 120. A gate oxide layer 130 is formed above channel region 120, and a conductive gate 140, such as a polysilicon gate, is formed on gate oxide layer 130.
To predict device performance, circuit designers typically employ "compact models" in the form of software, which characterize transistors, such as MOS devices, using a limited number of measured device electrical characteristics. The results of compact modeling are then used in circuit simulation to optimize the circuit. An important input for compact modeling is source/drain resistance; that is, the resistance carriers meet when they move from a source/drain region 110 to channel region 120. It is highly desirable to obtain an accurate measurement of source/drain resistance (Rds). However, Rds of an actual device cannot be measured directly using conventional techniques. Rather, the prior art typically derives Rds after measuring other electrical characteristics; e.g., the drain current of devices at different gate voltages.
One such prior art technique is illustrated in FIG. 2, wherein Rds is derived by comparing voltage and current measurements of a "nominal" device to those of a long channel device. As shown in FIG. 2, which graphs gate length along the x-axis and Rds along the y-axis, a particular gate voltage Vg' is selected, and the corresponding drain current IVg' is measured for different gate lengths, enabling calculation of Rds at each gate length to produce a line, as shown. Then, a different gate voltage Vg" is selected and the procedure repeated. In theory, the y-coordinate of the point where the lines associated with Ivg' and Ivg" cross is the desired value of RDS of a nominal device.
This technique produces an acceptably accurate value of Rds when the channel region of the device is uniformly doped. Disadvantageously, as device structures become more complex and channel regions are non-uniformly doped to optimize device performance (e.g., using retrograded doping profiles, pocket implants, HALO implants, etc.), the validity of such conventional techniques for deriving Rds no longer holds, and it becomes much more difficult to derive accurate Rds values.
There exists a need for a methodology for accurately measuring Rds of MOS devices directly, thereby enabling more accurate compact modeling of such devices and, consequently, facilitating device optimization.